1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same, and more specifically to a metal oxide semiconductor field effect transistor(MOSFET) which is formed on a silicon on insulator(SOI) substrate comprising a handling wafer, a buried insulating layer formed on the handling wafer and a silicon layer formed on the buried insulating layer.
2. Description of the Related Art
An SOI substrate generally includes a handling wafer, a silicon layer where a semiconductor device to be formed, and a buried insulating layer which is electrically isolated between the silicon layer and the handling wafer. In contrast to a bulk transistor which is formed on a single crystalline silicon substrate, a MOSFET formed on the SOI substrate does not need a well forming process. Also, since isolation layer of the SOI substrate comes into contact with the buried insulating layer, the active regions of the MOSFET are completely isolated, to thereby prevent the latch-up which is one of the problems in a CMOS transistor.
The SOI substrate can be also formed by a bonding method which bonds a silicon wafer having an insulating layer formed thereon to a handling wafer, or separation by implanted oxygen(SIMOX) method in which oxygen ions are deeply implanted into a silicon wafer to form a buried insulating layer.
A conventional semiconductor device using the SOI substrate is explained below with reference to FIG. 1. Referring to FIG. 1, a SOI substrate 10 includes a handling wafer 1, an insulating layer 2 and an impurity doped silicon layer 3. The silicon layer 3 of the SOI substrate 10 is the body of a MOSFET, which does not connected with any electrode. A gate insulating layer 4 and a polysilicon layer are sequentially formed on the silicon layer 3, and patterned, to form a gate electrode 5. Impurities having a conductivity type opposite to that of the silicon layer 3 are ion-implanted into a selected portion of the silicon layer 3, placed in both sides of the gate electrode 5, to form source/drain regions 6. Then, side-wall spacers 7 are formed on the side walls of gate electrode 5 by a well-known method. An intermediate insulating layer 8 is formed to a selected thickness on the overall surface of the substrate, and selectively etched to expose the source/drain regions 6. Metal lines 9 are formed on the intermediate insulating layer 8, to come into contact with the source/drain regions 6.
The aforementioned conventional semiconductor device formed on the SOI substrate has the following problems. When the semiconductor device is in a partial depletion state, holes generated in the drain region move to the silicon layer 4 whose potential is lower than that of the drain region, to be accumulated therein. The accumulation of hole in the silicon layer 3 increases the potential of the silicon layer 3, resulting in decrease in the threshold voltage of the semiconductor device. Furthermore, when the channel region of the MOSFET is saturated, moving charges in the channel come into collision with the molecules of the silicon lattice of the silicon layer 3. This generates a large amount of holes, which is called "impact ionization effect". Here, since the silicon layer 3 is floated, it is difficult to remove the large amount of holes from the SOI substrate 10. Accordingly, the large amount of holes flow to source/drain regions 6 by the electric field which is created during operation of the MOSFET. This brings about kink effect, increasing the drain current. The kink effect limits the circuit design of the MOSFET formed on the SOI substrate 10.